The embodiments described herein relate to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing a semiconductor device being capable of easily forming a hole type contact hole in a highly integrated semiconductor device and maximizing an open area of an active region.
So as to increase integration of the semiconductor device, various methods that integrate more circuit patterns in the limited area by modifying cell layout have been suggested. One of the methods is to modify an arrangement of the active regions which transistors are embedded therein from an 8F2 cell layout to a 6F2 cell layout.
In a DRAM, word lines are arranged to be orthogonally crossed to bit lines and active regions are repeatedly arranged to be obliquely crossed to the word line in the main axis direction of the active region in the 6F2 cell layout. The active regions of oblique patterns are arranged in rectangular patterns which are obliquely elongated to be crossed to the bit lines at an angle of about 27 degree.
As another method to increase integration of the semiconductor device, a recess gate or a buried gate has been used instead of the prior planar gate having a horizontal channel region.
In the buried gate structure, an isolation gate is used to form a bit line contact and a storage node contact in a line type. However, it increases a cell area of the chip dimension and a leakage current as compared with a conventional trench type isolation layer.
The more an integration of the semiconductor device is increased, the more the critical dimension (CD) of the contact hole pattern is reduced. Accordingly, it is difficult to define the contact hole pattern of a hole type on the mask and the active region is not open in etching process of the hole type contact hole. Furthermore, when the hole type contact is used, all the open area of the active region can not be used such that the contact resistance is increased.